The present disclosure relates to resonators, and specifically to resonators suitable for delta-sigma modulators.
In general, it is known that delta-sigma modulators used in analog-to-digital converters (ADCs) are capable of providing high accuracy and low power consumption by a noise shaping technique and an oversampling technique compared to Nyquist analog-to-digital converters. Among the delta-sigma modulators, continuous-time delta-sigma modulators are technically suitable for high-speed wide-band delta-sigma modulators. In a general continuous-time delta-sigma modulator, an input signal passes through cascade-connected n analog integrators, and then is quantized by a quantizer, an output of which is fed back by n digital-to-analog converters (DACs) (for example, see the following two references: Steven R. Norsworthy, Richard Schereier and Gabor C. Temes, “Delta-Sigma Data Converters Theory, Design and Simulation,” IEEE press 1997; H. Inose, Y. Yasuda, “A unity bit Coding Method by Negative Feedback,” Proceedings of the IEEE, November 1963).
In general, in order to improve the conversion accuracy of a delta-sigma modulator, the order of a loop filter has to be increased to remove quantization noise. In order to increase the order of the loop filter, integrators the number of which corresponds to the order of the loop filter may be cascade-connected. However, this requires many operational amplifiers, which may increase power consumption and the chip area. For this reason, the delta-sigma modulator preferably uses a resonator which achieves a multi-order transfer function with one operational amplifier. In a known example of such a resonator, a CR series circuit is connected to an inverting input terminal of an operational amplifier, and a twin T notch filter and another CR series circuit are inserted into a negative-feedback section of the operational amplifier (for example, see Japanese Patent Publication No. S62-183209).